A. Iwata, T. Morie, and M. Nagata
Merged Analog-Digital Circuits Using Pulse Modulation for Intelligent SoC Applications (Invited)
IEICE Trans. Fundamentals, Vol. E84-A, No. 2, pp. 486-496, 2001.
IEICE Trans. Online
M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata
Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits
IEEE J. Solid-State Circuits, Vol. 36, No. 3, pp. 539-549, March 2001.
S. Kinoshita, T. Morie, M. Nagata and A. Iwata
A PWM Analog Memory Programming Circuit for Floating-Gate
MOSFETs with 75us Programming Time and 11b Updating
Resolution
IEEE J. Solid-State Circuits, Vol. 36, No. 8, pp. 1286-1290, August, 2001.
T. Yamanaka, T. Morie, M. Nagata, and A. Iwata
A CMOS Stochastic Associative Processor Using PWM Chaotic Signals
IEICE Trans. Electronics, Vol. E84-C, No. 12, pp. 1723-1729, 2001.
IEICE Trans. Online
[International Conference]
M. Nagata, T. Ohmoto, J. Nagai, T. Morie, and A. Iwata
Test Circuits for Substrate Noise Evaluation in CMOS Digital ICs
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001),
A1.7, pp. 13-14, Jan. 2001, Yokohama.
Y. Murasaka, M. Nagata, T. Ohmoto, T. Morie, and A. Iwata
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation
Proc. Intern. Symp. Quality Electronic Design (ISQED2001),
4C.3, pp. 482-487, Mar. 2001, San Jose.
M. Nagata, T. Ohmoto, Y. Murasaka, T. Morie, and A. Iwata
Effects of Power-Supply Parasitic Components on Substrate Noise Generation in Large-Scale Digital Circuits
Symp. on VLSI Circuits, #15-1, pp. 159-162, June 2001, Kyoto.
A. Iwata, T. Morie, and M. Nagata
Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies (Invited)
Extended Abstracts of the 2001 Int. Conf. Solid State Devices and Materials
(SSDM2001), pp. 88-89, Tokyo, Sept. 26, 2001.
T. Morie, M. Miyake, M. Nagata, and A. Iwata
A 1-D CMOS PWM Cellular Neural Network Circuit
and Resistive-Fuse Network Operation
Extended Abstracts of the 2001 Int. Conf. Solid State Devices and Materials
(SSDM2001), pp. 90-91, Tokyo, Sept. 26, 2001.
(pdf, 643kB)
T. Morie, M. Nagata, and A. Iwata
Design of a Pixel-Parallel Feature Extraction
VLSI System for Biologically-Inspired Object Recognition Methods
Proc. International Symposium on Nonlinear Theory and its
Application (NOLTA2001), pp. 371-374, Zao, Oct. 31, 2001.
(pdf, 389kB)
T. Morie, T. Matsuura, M. Nagata, and A. Iwata
An Efficient Clustering Algorithm Using Stochastic Association Model
and Its Implementation Using Nanostructures
Neural Information Processing Systems (NIPS2001) Abstracts of Papers, pp. 56,
Vancouver, Canada, Dec. 4, 2001.
(pdf, 235kB)
Atushi Iwata,Takafumi Oomoto,Yoshitaka Murasaka and Makoto Nagata
Measurement and SimulationTechniques for Cross-talk Noise on Mixed Signal SoC
SEMI Technorogy Symposium(STS2001) Proceedings, session5 pp. 35-37,Chiba,Dec 5-7,2001.
T. Morie, M. Nagata and A. Iwata
An Analog-digital Merged Circuit Architecture Using PWM
Techniques for Bio-inspired Nonlinear Dynamical Systems,
in Tsutomu Miki, Ed.,
"Brainware: Bio-Inspired Architecture and its Hardware Implementation"
(FLSI Soft Computing Series-Volume 6),
Chapter 3, pp. 61-87, Singapore, World Scientific Publishing, 2001.