T. Yoshida, T. Mashimo, M. Akagi, A. Iwata, M. Yoshida and K. Uematsu,
A Design of Neural Signal Sensing LSI with Multi-Input Channels,
IEICE Trans. Fundamentals, Vol. E87-A, No. 2, pp. 376-383, Feb. 2004.
T. Morie, K. Murakoshi, M. Nagata and A. Iwata,
Pulse Modulation Techniques for Nonlinear Dynamical Systems and a CMOS Chaos Circuit with
Arbitrary 1-D Maps,
IEICE Trans. Electron., Vol. E87-C, No. 11, pp. 1856-1862. November, 2004.
T. Yoshida, M. Akagi, T. Mashimo, A. Iwata, M. Yoshida and K. Uematsu,
A Design of Wireless Neural-Sensing LSI,
IEICE Trans. Electronics, Vol. E87-C, No. 6, pp. 996-1002. June 2004.
T. Yoshimura and A. Iwata,
An analysis of interference in synchronous systems,.
IEICE Electronics,Express, Vol. 1, No. 15, pp. 465-471, 2004.
[International Conference]
T. Morie, T. Nakano, J. Umezawa, and A. Iwata,
Gabor-Type Filtering Using Transient States of Cellular Neural Networks,
Intelligent Automation and Soft Computing, Vol. 10, No. 2, pp. 95-104, 2004.
K. Korekado, T. Morie, O. Nomura, H. Ando, T. Nakano, M. Matsugu, and A. Iwata,
A VLSI Convolutional Neural Network for Image Recognition Using Merged/Mixed Analog-Digital Architecture,
Int. J. Fuzzy and Intelligent Systems, Vol. 15, No. 3/4, pp. 173-179, 2004.
T. Morie, J. Umezawa, and A. Iwata,
Gabor-Type Filtering Using Transient States of Cellular Neural Networks,
Intelligent Automation and Soft Computing, Vol. 10, No. 2, pp. 95-104, 2004.
M. Shiozaki, T. Mukai, M. Ono, M. Sasaki and A. Iwata,
A 2Gbps and 7-multiplexing CDMA Serial Receiver Chip for Highly Flexible Robot Control System,
2004 Symposium on VLSI Circuits,Digest of Technical Papers, pp. 194-197,Honolulu, Hawaii, June 17-19, 2004.
T. Morie, J. Umezawa, and A. Iwata,
A Pixel-Parallel Image Processor for Gabor Filtering Based on Merged Analog-Digital Architecture,
2004 Symposium on VLSI Circuits, Digest of Technical papers, pp. 212-213, #14-1, Honolulu,
Hawaii, June 18, 2004.
T. Morie, T. Nakano, J. Umezawa, and A. Iwata,
Gabor Filtering Using Cellular Neural Networks and its Application to Face/Object Recognition,
World Automation Congress, #IFMIP075, Seville, Spain, June 28-July 1, 2004.
K. Sasaki, T. Morie, and A. Iwata,
A Spiking Neural Network with Negative Thresholding and Its Application to Associative Memory,
2004 IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS2004), pp. III-89 - III-92, Hiroshima, July 25-28, 2004.
O. Nomura, T. Morie, K. Korekado, M. Matsugu, and A. Iwata,
A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight
Decomposition Int. Conf. on Knowledge-Based Intelligent Information and
Engineering Systems,
(KES'2004), Wellington, New Zealand, Sep 22-24, 2004.
T. Yoshida, T. Mashimo, M. Akagi, A. Iwata, M. Yoshida and K. Uematsu,
A Low Noise Amplifier using Chopper Stabilization for a Neural Sensor LSI,
Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials pp.148-149, Sep, 2004, Tokyo