D. Kosaka, M. Nagata, Y. Murasaka, A. Iwata
Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits
IEICE Trans. Electron., Vol. E90-A, No. 2, pp. 380-387, February 2007.
Y. Masui, T. Yoshida, M. Sasaki and A. Iwata
A 0.6V Supply Complementary Metal Oxide Semiconductor Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization,
Japanese Journal of Applied Physics, Vol. 46, No. 4B, pp. 2252-2256, 2007
T. Yoshida, N. Ishida, M. Sasaki and A. Iwata
Low-Voltage, Low-Phase-Noise Ring Voltage-Controlled Oscillator Using 1/f-Noise Reduction Techniques
Japanese Journal of Applied Physics, Vol. 46, No.4B, pp. 2257-2260, 2007.
A. Iwata, T. Yoshida, M. Sasaki
Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices
IEICE Trans. Electron., Vol. E90-C, No. 6, pp. 1149-1155, June 2007.
[International Conference]
M.Sasaki, M.Shiozaki, A.Mori, A.Iwata, and H.Ikeda
"12GHz Low-Area-Overhead Standing-Wave Clock Distribution with
Inductively-Loaded and Coupled Technique,"
ISSCC Digest of Technical Papers, pp.180-181, Feb 6, 2007, San Francisco
T. Sato, A. Inoue, T. Shiota, T. Inoue, Y. Kawabe, T. Hashimoto, T.Imamura,Y. Murasaka, M. Nagata,and A. Iwata
“On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Application,”
ISSCC Digest of Technical Papers, pp. 290-291, Feb 6, 2007, San Francisco.
H. Ando, S. Kameda, D. Arizono, N. Fuchigami, K. Kaya, M. Sasaki, and A. Iwata
PCA-based Object Detection/Recognition Chip for Wireless Interconnected 3-D Integration,
Solid State Devices and Materials, September 21 2007, Tsukuba, Ibaraki, Japan.
A. Toya, Y. Murasaka, T. Ohmoto and A. Iwata
Evaluation of Digital Crosstalk Noise on a Differential Input VCO,
Solid State Devices and Materials, September 20 2007, Tsukuba.
[解説論文]
岩田 穆 三次元集積のためのインダクタ対による無線インタコネクション
電子情報通信学会,Vol. 90, No. 10, pp. 864-870, 2007.